1. Field of the Invention
The present invention relates to signal converters, output amplifying devices, audio apparatuses, and transmitting and receiving systems.
2. Description of the Related Art
Speaker arrays are used as speaker systems that are suitably applicable to home theaters or audio and visual (AV) systems. Wavefront synthesis is applied to such speaker arrays. Such speaker arrays can also be used for playback or control of sound fields.
FIG. 22 shows an example of sound field control by a speaker array 10. The speaker array 10 includes many speakers (speaker units) SP1 to SPn. In this case, for example, the number n of speakers is 256, and the speakers have a bore diameter of several centimeters. The speakers SP1 to SPn are actually arranged two-dimensionally on a plane. In the explanations below, however, they are arranged in a straight line in the horizontal direction, for the sake of simplification.
Audio signals are supplied from a signal source SC to delay circuits DL1 to DLn to be delayed by predetermined delay times τ1 to τn. The delayed audio signals are supplied to the corresponding speakers SP1 to SPn via corresponding power amplifiers PA1 to PAn. The delay times τ1 to τn for the delay circuits DL1 to DLn will be described below.
At any point, sound waves output from the speakers SP1 to SPn are synthesized and a sound pressure corresponding to the synthesized result can be acquired. Methods for setting a desired point in the sound field defined by the speakers SP1 to SPn shown in FIG. 22 as an increased sound pressure point Ptg, which is a point where the sound of the sound source SC is desired to be heard and is a point where sound pressure is higher than the surroundings, in other words, a point where sound pressure is increased, are broadly categorized into two methods shown in FIGS. 22 and 23.
The method shown in FIG. 22 is called a “focus type”. In this case, the delay times τ1 to τn for the delay circuits DL1 to DLn are set to:τ1=(Ln−L1)/s, τ2=(Ln−L2)/s, τ3=(Ln−L3)/s, ...τn=(Ln−Ln)/s=0,where L1 to Ln represent distances from the speakers SP1 to SPn to the increased sound pressure point Ptg and s represents a sound velocity.
The audio signals output from the signal source SC are converted into sound waves and output delayed by the times τ1 to τn represented by the above equations from the speakers SP1 to SPn. Thus, all the sound waves reach the increased sound pressure point Ptg at the same time, and the sound pressure of the increased sound pressure point Ptg is larger than the surroundings.
In other words, in the system shown in FIG. 22, time differences between the sound waves caused by differences between path lengths from the speakers SP1 to SPn to the increased sound pressure point Ptg are compensated for by the delay circuits DL1 to DLn, so that sounds are focused on the increased sound pressure point Ptg.
The method shown in FIG. 23 is called a directional type. In this case, the delay times τ1 to τn for the delay circuits DL1 to DLn are set so that traveling waves (sound waves) output from the speakers SP1 to SPn have the same phase wavefront. Thus, the directivity is provided for the sound waves, and the directivity is in the direction of the increased sound pressure point Ptg. This system can also be regarded as a case where the distances L1 to Ln are infinite in the system of the focus type.
Each of power amplifiers PA1 to PAn used for the speaker array 10 may be class D power amplifiers. Each of the class D power amplifiers performs power amplification by switching operation and is arranged as shown in FIG. 24. In the class D power amplifier shown in FIG. 24, four output switching elements are bridge-connected to a speaker such that an output stage is arranged in a full-bridge configuration.
In other words, a digital audio signal Pin is supplied to a ΔΣ modulation circuit 12 via an input terminal 11 to be converted into a digital audio signal in which quantization noise in an audible band is suppressed and the number of bits is reduced, for example, the number of quantization bits is six. The digital audio signal is supplied to pulse width modulation (PWM) circuits 13A and 13B to be converted into a pair of PWM signals PA and PB, as shown in FIG. 25.
In this case, the pulse widths of the PWM signals PA and PB change in accordance with the level indicated by the input signal Pin (the level of an analog signal as the signal Pin for each sample, and the same applies to the following descriptions). Also, as shown in FIG. 25, the pulse width of the PWM signal PA corresponds to the level indicated by the input signal Pin, and the pulse width of the PWM signal PB corresponds to a 2's complement of the level indicated by the input signal Pin. Furthermore, rising edges of the PWM signals PA and PB are fixed at a starting point of a cycle period (reference period) Tc of the PWM signals PA and PB, and falling edges of the PWM signals PA and PB change in accordance with the level indicated by the input signal Pin.
The carrier frequency fc (=1/Tc) of each of the PWM signals PA and PB is, for example, sixteen times the sampling frequency fs of the input digital audio signal Pin. If the sampling frequency fs is 48 kHz, the following carrier frequency fc can be obtained:fc=16fs=16×48 kHz=768 kHz.
The PWM signal PA is supplied to a drive amplifier 14A, and a pair of drive voltage VA+ having the same level as the signal PA and drive voltage VA− having the inverted level of the signal PA are generated, as shown in FIG. 25 and Part A of FIG. 26. The drive voltages VA+ and VA− are supplied to the gates of a pair of n-channel metal oxide semiconductor-field effect transistors (MOS-FETs) Q11 and Q12, respectively. The FETs Q11 and Q12 constitute a push-pull circuit 15A. The drain of the FET Q11 is connected to a power line of a positive power supply voltage +VDD, and the source of the FET Q22 is connected to the drain of the FET Q12. The source of the FET Q12 is connected to a power line of a negative power supply voltage −VDD.
The source of the FET Q11 and the drain of the FET Q12 are connected to one end of a speaker SP via a low-pass filter 16A.
Also, processing for the PWM signal PB from the PWM circuit 13B is similar to that for the PWM signal PA. In other words, when the PWM signal PB is supplied to a drive circuit 14B, a pair of drive voltage VB+ having the same level as the signal PB and drive voltage VB− having the inverted level of the signal PB are generated, as shown in Part B of FIG. 26. The drive voltages VB+ and VB− are supplied to the gates of a pair of n-channel MOS-FETs Q13 and Q14, respectively, that constitute a push-pull circuit 15B.
The source of the FET Q13 and the drain of the FET Q14 are connected to the other end of the speaker SP via a low-pass filter 16B.
Thus, when the voltage VA+ is high (H) and the voltage VA− is low (L), since the FET Q11 is turned on and the FET Q12 is turned off, a voltage VA of a node between the FETs Q11 and Q12 is +VDD, as shown in Part C of FIG. 26. In contrast, when the voltage VA+ is low and the voltage VA− is high, since the FET Q11 is turned off and the FET Q12 is turned on, the voltage VA is −VDD.
Similarly, when the voltage VB+ is high and the voltage VB− is low, since the FET Q13 is turned on and the FET Q14 is turned off, a voltage VB of a node between the FETs Q13 and Q14 is +VDD, as shown in Part D of FIG. 26. In contrast, when the voltage VB+ is low and the voltage VB− is high, since the FET Q13 is turned off and the FET Q14 is turned on, the voltage VB is −VDD.
During a period when the voltage VA is +VDD and the voltage VB is −VDD, a current i flows from the node between the FETs Q11 and Q12 to the node between the FETs Q13 and Q14 via a line including the low-pass filter 16A, the speaker SP, and the low-pass filter 16B, in that order, as shown in FIG. 24 and Part E of FIG. 26.
During a period when the voltage VA is −VDD and the voltage VB is +VDD, the current i flows from the node between the FETs Q13 and Q14 to the node between the FETs Q11 and Q12 via a line including the low-pass filter 16B, the speaker SP, and the low-pass filter 16A, in that order. During a period when the voltages VA and VB are +VDD and during a period when the voltages VA and VB are −VDD, the current i does not flow. In other words, the push-pull circuits 15A and 15B constitute a balanced transformerless (BTL) circuit.
The period when the current i flows changes in accordance with the period when the PWM signal PA or PB rises. Also, the current i is integrated by the low-pass filters 16A and 16B when the current i flows in the speaker SP. Thus, the current i flowing in the speaker SP is an analog current corresponding to the level indicated by the input signal Pin and is a power-amplified current. In other words, power-amplified output is supplied to the speaker SP.
Accordingly, the circuit shown in FIG. 24 operates such that the output stage functions as a full-bridge class D power amplifier. Since the FETs Q11 to Q14 perform power amplification by switching the power supply voltage between +VDD and −VDD, an enhanced power efficiency can be achieved. Thus, in the speaker array 10 that requires the many power amplifiers PA1 to PAn, the amplifier shown in FIG. 24 is suitable as the power amplifiers PA1 to PAn.
FIG. 27 shows a case where an output stage of a class D power amplifier is arranged in a half-bridge configuration in which a pair of switching elements is connected in series with each other such that output is acquired from a connection middle point of the switching elements. In this case, the voltage VA shown in Part C of FIG. 26 is acquired at the node between the FETs Q11 and Q12, and the voltage VA is supplied to the speaker SP via the low-pass filter 16A.
Thus, in the amplifier described above, power-amplified output is also supplied to the speaker SP. Also, since power amplification is performed by switching the power supply voltage between +VDD and −VDD, an enhanced power supply efficiency can be achieved. Thus, in the speaker array 10 that requires the many power amplifiers PA1 to PAn, the amplifier shown in FIG. 27 is suitable as the power amplifiers PA1 to PAn.
An example of the known technology is disclosed in Japanese Unexamined Patent Application Publication No. 9-233591.
When the power amplifiers PA1 to PAn for the speaker array 10 are class D power amplifiers, as described above, the class D power amplifiers PA1 to PAn are connected to the speakers SP1 to SPn, as shown in FIG. 28A or 28B (FIGS. 28A and 28B show the speakers SP1 to SPn from the rear side, in other words, FIGS. 28A and 28B are illustrations viewed from a connection terminal side). For the sake of simpler explanation, four speakers SP1 to SP4 constitute the speaker array 10 and the speakers SP1 to SP4 are arranged in a two-row by two-column matrix, as shown in FIG. 29 (FIG. 29 is an illustration viewed from the front side).
When the amplifiers PA1 to PA4 are arranged in a full-bridge configuration, as shown in FIG. 24, eight speaker cables are needed, as shown in FIG. 28A. When the amplifiers PA1 to PA4 are arranged in a half-bridge configuration, as shown in FIG. 27, five speaker cables are needed, as shown in FIG. 28B. In other words, when the output stage including n output amplifiers PA1 to PAn is arranged in a full-bridge configuration, 2 n speaker cables are required. When the output stage including n output amplifiers PA1 to PAn is arranged in a half-bridge configuration, (n+1) speaker cables are required.
Thus, when n represents 256, if the power amplifiers PA1 to PA256 are arranged in a full-bridge configuration, 512 speaker cables must be routed. Also, if the power amplifiers PA1 to PA256 are arranged in a half-bridge configuration, 257 speaker cables must be routed. Routing such a large number of cables is troublesome, and is not practical.
If a part including the delay circuits DL1 to DL256 and the power amplifiers PA1 to PA256 shown in FIG. 22 or 23 are arranged in a speaker box, only two cables (a pair of cables) for supplying an audio signal from the signal source SC to the speaker box appear outside the speaker box. In this case, however, the number of cables between the power amplifiers PA1 to PA256 and the speakers SP1 to SP256 inside the speaker box is still large. This involves tremendous amount of time and labor for wiring and assembling.